1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly to a method of forming an interlayer dielectric film for multi-layered interconnections.
2. Description of the Prior Art
A method described in Japanese Patent Laid-Open No. Hei 2-209753 will be described with reference to FIGS. 1A to 1D as a method of forming an interlayer dielectric film for conventional multi-layered interconnections.
As shown in FIG. 1A, lower level aluminum wirings 4a are formed on a silicon substrate 1a.
As shown in FIG. 1B, a plasma-enhanced CVD-SiO.sub.2 film (hereinafter called PECVD-SiO.sub.2 film) 6b having a thickness of 0.2 to 0.3 .mu.m is formed on the resultant structure. A 2 .mu.m thick TEOS-based SiO.sub.2 film 7a is deposited by an atmospheric pressure CVD (Chemical Vapor Deposition) method using TEOS and ozone at 350.degree. C. (hereinafter called TEOS-Ozone SiO.sub.2 film). TEOS is represented by a chemical formula of Si(OC.sub.2 H.sub.5).sub.4 and is called a tetraethylorthosilicate or tetraethoxysilane.
As shown in FIG. 1C, a plasma-enhanced CVD-SiO.sub.2 film 8a is deposited on the resultant structure again, and a resist 9 is formed and patterned.
As shown in FIG. 1D, the plasma-enhanced CVD-SiO.sub.2 film 8a, the TEOS-Ozone SiO.sub.2 film 7a, and the PECVD-SiO.sub.2 film 6b are etched using the resist 9 as a mask to form through holes. After upper level aluminum wirings 14a are formed, the resultant structure is annealed at 380.degree. C. to properly electrically connect the upper aluminum wirings 14a to the lower level aluminum wirings 4a.
When a lower wiring is formed on the surface of a semiconductor substrate, the substrate surface feature is reflected more or less upon the interlayer dielectric films surface on the lower level wirings by the CVD method. Therefore, it is difficult to planarize the surface of the resultant device by only using the CVD method.
A-wiring metal may be left in the recess during the wirings formation and is short-circuited with the same level wirings. In addition, the upper level wirings are disconnected to form open circuits. Short-circuiting occurs or the open circuit is formed to reduce the product yield.
Step coverage of the upper level wiring becomes poor causing stress migration or electromigration. The upper level wiring tends to be disconnected thereby degrading the reliability of the multi-layered interconnections.
A silicon oxide film deposited by the conventional CVD method using TEOS and ozone has a high moisture content. Moisture is evaporated from the side surface of a through hole to increase a connection resistance during deposition of a metal film serving as the upper level wiring. For this reason, the yield of the multilayered interconnections is reduced and their reliability is degraded.
When a multi-layered interconnection having three or more layers is formed, an absolute step height between a portion having no interconnection and a portion in which interconnections overlap each other is increased. In the manufacturing process of patterning a photo-resist on the semiconductor substrate, the dimensional precision of the resist pattern is thus degraded.
It is therefore difficult to form a micropatterned and multi-layered interconnection.